Group: Aatmesh Shrivastava and Alicia Klinefelter
Technology: IBM 130
Date of Last Revision: Dec. 06, 2010

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************ The figures in the final report will be referenced by their figure number within the paper. ************
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Figure 1: Power with Respect to Frequency in a Crystal Oscillator.
Netlist used: Study carried out on crystal oscillator.

Figure 3: Frequency-to-Voltage Converter.
Netlist used: FVC

Figure 8: ADC Converging Input Voltage for Input of 381mV.
Netlist used: SAR_ADC_netlist

Figure 10: a) Transient behavior b) steady state output of VCO
Netlist used: Frequency_locked_loop

Figure 11: PTAT circuit and its output
Netlist used: PTAT

Figure 12:  a) ZTC current, 7b) VCO output at 0, 50 and 100oC
Netlist used: a) PTAT b) VCO

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*************   A general description of netlists included in folder.                                      **************************
*************   The simple logic gates (and, nand, or, inverter, etc) are not included in the directory.   **************************
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ADC_and_DAC_netlist     :   The ADC and the DAC interacting with eachother. The "done" signal from the ADC is used
				to trigger the registers to store the incoming data. This signal is also used to control
			       the header for the ADC that cuts off its power supply once the conversion has completed.

analog_demux_netlist    :   An analog demux that uses transmission gates. This is used for the DAC blocks. A pass gate is
			       used for one channel of the demux since the input should always go to ground in certain cases.

Cap_DAC_netlist	   :   The charge scaling DAC that uses binary weighted capacitors (mimcaps in this technology).  

comparator_netlist      :   A simple comparator that uses the NMOS and PMOS opamps (listed in this directory). It uses a reference
				voltage of 500mV and has a gain around 100. Stability is not an issue due to its open-loop structure.

D_latch_netlist	   :   A level sensitive (transparent when clock is high) latch D latch used to create the registers used within this directory.

DFF_netlist 		   :   A positive-edge triggered D flip-flop using a two D latches in a master-slave configuration.

DFF_with_reset_netlist  :   A positive-edge triggered D flip-flop as the one above, yet it also has a reset capability. This is used in the ADC.

NMOS_opamp_netlist	   :   A single-stage opamp with an differential stage using NMOS transistors and a PMOS current mirror load. Used for
				the comparator.

PMOS_opamp_netlist	   :   A single-stage opamp with an differential stage using PMOS transistors and a NMOS current mirror load. Used for
				the comparator.

R2R_DAC_netlist	   :   A DAC used for the final output voltage coming out of the retention stage. Uses nwell resistors to create 
				voltage division network. Current controlled in each branch by increasing the size of the transistors.

SAR_ADC_netlist	   :   The final SAR ADC with comparator, capacitor DAC, up counter, frequency division network, and SAR logic block.

SAR_logic_netlist	   :   The SAR logic block for the SAR ADC. It takes the result from the comparator and sets the bit outputs for the system.
				It also sets up the next input for the DAC.

TFF_netlist	          :	A T flip-flop used for the up counter in the ADC as well as the frequency division in the ADC.

tgate_netlist		   :   A transmission gate used throughout various designs. An inverter is included within the schematic to invert
				the control signal attached to the PMOS.

up_counter_netlist	   :	A 4-bit up counter used in the ADC for counting to 10. Once it has reached ten, the conversion is completed
				and this result is used to assert the "done" signal.

*********************************************************** .scs Files ********************************************************************

FVC                      :  Netlist of frequency to voltage converter

TB_FVC                   :  Test_Bench to test Frequency to voltage converter

OPAMP                    :  Netlist of Operational Amplifier

TB_OPAMP                 :  Test bench to test Operational Amplifier

VCO                      :  Netlist of Voltage controlled Oscillator

TB_VCO                   :  Test bench for testing Voltage controlled Oscillator

Frequency_locked_loop    : A frequency locked loop is the negative feedback structure using OPAMP, VCO and FVC.Netlist of that

TB_Frequency_locked_loop : Test bench for FLL.

Top_level                : Netlist of complete set up

TB_Top_level             : Test bench for top level circuit 

PTAT                     : PTAT circuit netlist

TB_PTAT                  : PTAT testbench


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Please go through our presentation and document to understand the details of the circuit. 

You can contact as4xz@virginia.edu and amk5vx@virginia.edu for more details

Link to Wiki Project Page: https://venividiwiki.ee.virginia.edu/twiki/bin/view/Main/ClassECE6332Fall10GroupClockGenerator
